Q21

Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a $32\text{-bit}$ register $\text{R1}$. The effective address of the memory location is obtained by the addition of a constant $20$ and the contents of register $\text{R2}$. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?