Q28

The $\text{TLB}$ performs an associative search in parallel on all its valid entries using page number of incoming virtual address.

If the virtual address of a word given by $\text{CPU}$ has a $\text{TLB}$ hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory.

The memory access time using a given inverted page table is always same for all incoming virtual addresses.

In a system that uses hashed page tables, if two distinct virtual addresses $\text{V1}$ and $\text{V2}$ map to the same value while hashing, then the memory access time of these addresses will not be the same.