Q79

Consider the following data path of a $\text{CPU}.$

The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the $\text{ALU}.$ Two clock cycles are needed for memory read operation – the first one for loading address in the $\text{MAR}$ and the next one for loading data from the memory bus into the $\text{MDR}.$ The instruction $``\text{add R0, R1}”$ has the register transfer interpretation $\text{R0} \Leftarrow \text{R0 + R1}.$ The minimum number of clock cycles needed for execution cycle of this instruction is: