Q68

A $5$ stage pipelined CPU has the following sequence of stages: IF – instruction fetch from instruction memory RD – Instruction decode and register read EX – Execute: ALU operation for data and address computation MA – Data memory access – for write access, the register read at RD state is used. WB – Register write back Consider the following sequence of instructions: $I_1$: $L$ $R0, loc$ $1$; $R0 \Leftarrow M[loc1]$ $I_2$: $A$ $R0$, $R0$; $R0 \Leftarrow R0 +R0$ $I_3$: $S$ $R2$, $R0$; $R2 \Leftarrow R2-R0$ Let each stage take one clock cycle. What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$?