Q50

The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let $t_{E X}$ denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of $t_{E X}$ and $M$ (the number of instructions of that type in a sequence of $100$ instructions for a program P ), are given in the table below. The duration of the pipeline clock cycle is $1$ nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible.

\renewcommand{\arraystretch}{1.3} \begin{array}{|l|c|c|} \hline \text{Instruction} & \begin{array}{c} t_{EX}\ \text{in} \\ \text{nanoseconds} \end{array} & M \\ \hline \text{LOAD} & 1.8 & 15 \\ \hline \text{IMUL} & 1.5 & 10 \\ \hline \text{IDIV} & 2.5 & 5 \\ \hline \text{FADD} & 1.7 & 10 \\ \hline \text{FSUB} & 1.7 & 5 \\ \hline \text{FMUL} & 2.8 & 15 \\ \hline \text{FDIV} & 3.2 & 5 \\ \hline \begin{array}{l} \text{All other} \\ \text{instructions} \end{array} & \begin{array}{c} \text{Less than} \\ 1.0 \end{array} & 35 \\ \hline \end{array}

When program $\text{P}$ is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is $\_\_\_\_$. (answer in integer)