Q51

A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instructions are equally divided into two types, namely $\text{R}$-type and $\text{I}$-type, whose formats are shown below. R - type Instruction Format: \begin{array}{|l|l|l|l|l|} \hline OPCODE & UNUSED & DST Register & SRC Register1 & SRC Register 2 \\ \hline \end{array} I - type Instruction Format: \begin{array}{|l|l|l|l|} \hline OPCODE & DST Register & SRC Register & \# Immediate value/address \\ \hline \end{array} In the $\text{OPCODE}$, $1$ bit is used to distinguish between $\text{I}$-type and $\text{R}$-type instructions and the remaining bits indicate the operation. The processor has $50$ architectural registers, and all register fields in the instructions are of equal size. Let $\text{X}$ be the number of bits used to encode the $\text{UNUSED}$ field, $\text{Y}$ be the number of bits used to encode the $\text{OPCODE}$ field, and $\text{Z}$ be the number of bits used to encode the immediate value/address field. The value of $\text{X+2Y+Z}$ is __________.