Q18

MCQMarks unknown

Design a 2K $\times$ 8 (2048 locations, each 8 bit wide) memory system mapped at addresses (1000) $_{16}$ to (17FF) $_{16}$ for the 8085 processor using four 1K $\times$ 4 memory chips. Each of these chips has the following signal pins:

(A)

$\overline{CS}$ (Chip select, data lines are in high impedance state when it is 1)

(B)

$\overline{RD}$ (0 for read operation)

(C)

$\overline{WR}$ (0 for write operation)

(D)

$A_0, A_1, \dots A_9$ (input address lines. $A_0$ is the lest significant)

(E)

$D_0, D_1, D_2, D_3$ (bi-directional data lines. $D_0$ is the least significant)

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