Q17

Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers $R1, R2$ and $R3$. The meanings of the instructions are shown by comments (starting with ;) after the instructions. X: CMP R1, 0; Compare R1 and 0, set flags appropriately in status register JZ Z; Jump if zero to target Z MOV R2, R1; Copy contents of R1 to R2 SHR R1; Shift right R1 by 1 bit SHL R1; Shift left R1 by 1 bit CMP R2, R1; Compare R2 and R1 and set flag in status register JZ Y; Jump if zero to target Y INC R3; Increment R3 by 1; Y: SHR R1; Shift right R1 by 1 bit JMP X; Jump to target X Z:...