Q13

An instruction pipeline consists of $4$ stages – Fetch $(F)$, Decode field $(D)$, Execute $(E)$ and Result Write $(W)$. The $5$ instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the table below

$$\begin{array}{|c|c|c|c|c|} \hline \textbf{Instruction} & \textbf {F} &\textbf {D} & \textbf {E} & \textbf{W } \\\hline \textbf{1}& 1 & 2 & 1 & 1 \\\hline \textbf{2} & 1 & 2 & 2 & 1\\\hline \textbf{3}& 2 & 1 & 3 & 2 \\\hline \textbf{4} & 1 & 3 & 2 & 1 \\\hline \textbf{5} & 1 & 2 & 1 & 2 \\\hline \end{array}$$

Find the number of clock cycles needed to perform the $5$ instructions.