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← GATE CSE 2017 Set 1

Q25

NAT1 mark

Consider a two-level cache hierarchy with L1L1 and L2L2 caches. An application incurs 1.41.4 memory accesses per instruction on average. For this application, the miss rate of L1L1 cache is 0.10.1; the L2L2 cache experiences, on average, 77 misses per 10001000 instructions. The miss rate of L2L2 expressed correct to two decimal places is ________.

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