Q12

Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle and all writes occur in the first phase. Consider the execution of the following instruction sequence:

$$\begin{array}{|l|l|} \hline \text{I1:} & \text{sub $r 2,r 3,r 4$} & \text{/*}\quad r2 \leftarrow r3 - r4 \quad\text{*/} \\\hline \text{I2:} & \text{sub $r 4,r 2,r 3$} & \text{/*}\quad r4 \leftarrow r2 - r3 \quad\text{*/} \\\hline \text{I3:} & \text{sw $r2,100(r1)$} & \text{/*}\quad\text{$M[r1 + 100]$} \leftarrow \text{r2} \quad\text{*/}\\\hline \text{I4:} & \text{sub $r 3,r 4,r 2$} & \text{/*}\quad r3 \leftarrow r4 - r2 \quad\text{*/} \\\hline\end{array}$$