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← GATE CSE 1996

Q5

NATMarks unknown

A logic network has two data inputs AA and BB, and two control inputs C0C_0 and C1C_1. It implements the function FF according to the following table.

C1C0F00A+B‾01A + B10A⊕B{\begin{array}{|cc|c|}\hline C_1& C_0& \textbf{F}\\\hline 0&0&\overline{A + B} \\ 0&1& \text{A + B} \\ 1&0& A \oplus B \\ \hline \end{array}}

Implement the circuit using one 4 to 1 Multiplexer, one 2-input Exclusive OR gate, one 2-input AND gate, one 2-input OR gate and one Inverter.

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