Q06,a,b

A microprocessor is capable of addressing 1 megabyte of memory with a 20-bit address bus. The system to be designed requires 256 K bytes of RAM, 256 K bytes of EPROM, 16 I/O devices (memory mapped I/O) and 1 K byte of EERAM (electrically erasable RAM). (a) Design a memory map (to reduce decoding logic) and show the decoding logic if the components available are: Type Size Speed RAM 6 K x 8 140 ns EPROM 256 K x 8 150 ns EERAM 256 x 8 500 ns - read, 3 microsec - write (b) The microprocessor is operating at 12.5 mHz and provides time equivalent to two clock cycles for memory read and write. Assuming control signals similar to 8085, design the extra logic required for interfacing EERAM.