Q05,b

Three devices $A, B$ and $C$ are connected to the bus of a computer, input/output transfers for all three devices use interrupt control. Three interrupt request lines INTR$1,$ INTR$2$ and INTR$3$ are available with priority of INTR$1 >$ priority of INTR$2 >$ priority of INTR$3.$ Draw a schematic of the priority logic, using an interrupt mask register, in which Priority of $A$ > Priority of $B$ > Priority of $C.$