Q53

Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$, and $\text{Write Back } \textsf{(WB)}$. Each stage of the pipeline, except the $\textsf{EX}$ stage, takes one cycle. Assume that the $\textsf{ID}$ stage merely decodes the instruction and the register read is performed in the $\textsf{EX}$ stage. The $\textsf{EX}$ stage takes one cycle for $\textsf{ADD}$ instruction and two cycles for $\textsf{MUL}$ instruction. Ignore pipeline register latencies. Consider the following sequence of $8$ instructions:

$$\textsf{ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL}$$

Assume that every $\textsf{MUL}$ instruction is data-dependent on the $\textsf{ADD}$ instruction just before it and every $\textsf{ADD}$ instruction (except the first $\textsf{ADD}$) is data-dependent on the $\textsf{MUL}$ instruction just before it. The $\textit{speedup}$ defined as follows.

$$\textit{Speedup} = \dfrac{\text{Execution time without operand forwarding}}{\text{Execution time with operand forearding}}$$

The $\textit{Speedup}$ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________