Q23

A $32\text{-bit}$ wide main memory unit with a capacity of $1\;\textsf{GB}$ is built using $256\textsf{M} \times 4\text{-bit}$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The time taken to perform one refresh operation is $50\;\text{nanoseconds}$. The refresh period is $2\;\text{milliseconds.}$ The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.