Q06,a

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Using $\text{D}$ flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines:

(A)

Clock $\text{CLK}$

(B)

Three parallel data inputs $A, B, C$

(C)

Serial input $S$

(D)

Control input $\text{LOAD} / \overline{\text{SHIFT}}$ .

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