Q47

A non-pipelined instruction execution unit that operates at $1.6$ GHz clock takes an average of $5$ clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at $1.2$ GHz due to pipeline overheads. While executing a program in the pipelined design, $30 \%$ of instructions encountered a stall of $2$ cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is $\_\_\_\_\_\_\_$ (rounded off to two decimal places) Note: $1 \mathrm{G}=10^{9}$