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Q32

MCQ2 marks, −0.67

A 44 kilobyte (KB)\text{(KB)} byte-addressable memory is realized using four 1 KB1 \mathrm{~KB} memory blocks. Two input address lines (IA4 and IA3)\text{(IA4 and IA3)} are connected to the chip select (CS)\text{(CS)} port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11-IA0\text{IA11-IA0} are connected to the address port of these blocks. The chip select (CS)\text{(CS)} is active high.

Figure 1

The input memory addresses (IA11-IA0),\text{(IA11-IA0)}, in decimal, for the starting locations (Addr = 0)\text{(Addr = 0)} of each block (indicated as X1, X2, X3, X4\text{X1, X2, X3, X4} in the figure) are among the options given below. Which one of the following options is CORRECT?\text{CORRECT}?

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