Q54

A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, $2$ valid bits, $1$ modified bit and $1$ replacement bit. The number of bits in the tag field of an address is