Q77

Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD $R2 \leftarrow R7 + R8$ I2: Sub $R4 \leftarrow R5 – R6$ I3: ADD $R1 \leftarrow R2 + R3$ I4: STORE Memory $[R4] \leftarrow R1$ BRANCH to Label if $R1 == 0$ Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any program modification?